1. Field of the Invention
The present invention relates to a reticle used for step and repeat exposure, to method and apparatus of exposure using the reticle, and to semiconductor device.
2. Description of the Background Art
Reduction type projection printing has been known as an apparatus of projection exposure for transferring a pattern drawn on a reticle to a resist. In reduction type projection printing, step and repeat method is used, and a mechanism for realizing this method is provided.
The step and repeat method refers to a method of transferring a reticle pattern to a resist in which exposure is performed every time a wafer on a two-dimensionally movable X-Y stage is fed by a given distance. The method of exposure by the reduction type projection printing will be described in the following.
FIG. 14 shows a manner of exposure by a conventional reduction type projection printing apparatus. Referring to FIG. 14, a beam (g-line or i-line) from a mercury lamp is directed from a light source 51 through a condenser lens 50 to a glass mask (reticle) 210. The beam passed through reticle 21 is projected on a photoresist on a wafer 20 through a reduction projection lens 40.
In such a reduction type projection printing apparatus, an area which can be exposed at one time (one shot) is about 20 mm.times.20 mm, for example. Position of wafer 20 is automatically moved successively in X, Y direction by an X-Y stage 52, and wafer 20 is exposed shot by shot.
Wafer 20 is vacuum fixed on X-Y stage 52.
Structure of a conventional reticle used for reduction type projection printing will be described.
FIG. 15 is a schematic plan view showing the structure of the conventional reticle. FIGS. 16 and 17 are partial plan views showing, in enlargement, areas P5 and P6 of FIG. 15.
Referring to FIG. 15, a structure of a reticle 210 having two circuit patterns corresponding to two chips formed in one shot is shown. More specifically, element forming regions 1A and 1B each correspond to a circuit pattern of one chip. A dicing region 3B is arranged between element forming regions 1A and 1B. Element forming regions 1A and 1B as well as dicing region 3B constitute a prescribed region 2 having a rectangular planar shape.
Referring to FIGS. 15 and 16, a relatively wide dicing region 203A is arranged outside and to be in contact with left and lower sides in the figure of the prescribed region 2. In the wide dicing region 203A, monitor mark regions, that is, alignment mark regions 5 and registration accuracy measurement marks 7 are arranged at an upper left corner, a lower left corner and a lower right corner in the figure of prescribed region 2. Further, monitor mark regions 5 and 7 are also arranged in dicing region 3B.
Referring to FIGS. 15 and 17, a relatively thin dicing region 203C is arranged on right and upper sides in the figure, outside prescribed region 2.
Referring to FIGS. 15 to 17, an overlap region (slit region) 204 is arranged in contact with each of the relatively wide dicing region 203A and narrow dicing region 203C and surrounding outer peripheries of the dicing regions. Overlap region 204 is provided in consideration of step offset experienced during step and repeat exposure. A light intercepting region 9 is arranged on an outer peripheral region of dicing regions 203A, 203C and overlap region 204.
A cross section of the conventional reticle taken along the line A3--A3 of FIG. 16, for example, is as shown in FIG. 18A. Referring to FIG. 18A, reticle 210 includes a transparent substrate 11, and light intercepting films 13 and 15 formed on transparent substrate 11. Though not shown in the figure, a prescribed circuit pattern is formed by a light intercepting film, in element forming regions 1A and 1B. In alignment mark region 5, a plurality of alignment mark patterns 13 formed of the light intercepting film are arranged. A light intercepting film 15 is formed entirely over the outermost light intercepting region 9.
Process steps up to patterning of a film to be etched of the wafer using the conventional reticle will be described in the following.
The exposure beam which is transmitted through reticle 210 shown in FIG. 15 is directed to the photoresist applied on the wafer, and exposure of one shot is completed. Thereafter, stage 52 on which wafer 20 is mounted moves as shown in FIG. 14, and the next shot is exposed. This time, exposure is performed such that overlap region 204 (FIGS. 16, 17) of the already exposed shot is overlapped with the overlap region 204 of the shot which is to be newly exposed. This is to prevent any region from being left unexposed between adjacent shots because of step offset which occurs during step and repeat exposure.
In this manner, a plurality of shots 260 are exposed on the photoresist as shown in FIG. 19. This shot 260 includes, corresponding to reticle 210 shown in FIG. 15, element forming regions 61A and 61B, relatively wide dicing regions 263A and 263B, a relatively narrow dicing region 263c (not shown), an alignment mark region 65 and a registration accuracy measurement mark region 67. FIG. 19 shows a state in which four shots are exposed. After exposure of each shot 260 onto a photoresist is completed as shown in FIG. 19, the photoresist is developed and the resist pattern is formed.
FIG. 18B corresponds to a cross section taken along the line B3--B3 of FIG. 19 of a wafer corresponding to the reticle of FIG. 18A. Referring to FIG. 18B, when the photoresist 27 is of positive type, only non-exposed regions of photoresist 27 are left by development. Using resist pattern 27 as a mask, underlying film 23 to be etched is etched, and film 23 is patterned to a desired shape. Thereafter, resist pattern 27 is removed. Here, an example is shown in which a protruding alignment mark 23 is formed on a semiconductor substrate 21 in alignment mark region 65.
In FIG. 18B, photoresist 27 is not left at a region corresponding to light intercepting region 9 on the wafer, as part of the element forming region 61B and the dicing region of neighboring shot are positioned on this region.
Generally, in order to superpose the reticle pattern and the wafer pattern with high accuracy, reticle position is aligned with the wafer position. This alignment is more specifically performed by recognizing position of the alignment mark on the wafer by using diffracted beam, for example, determining shot rotation, reduction ratio and the like based on the recognition, and registering the position of the wafer alignment mark with the position of the reticle alignment mark.
In the conventional reticle, however, it is not possible to place alignment mark 5 near an upper right corner of the prescribed region 2 in FIG. 15. Therefore, position offset information at this corner is missed. Accordingly, positional offset (that is, error in shot magnification, error in shot rotation or the like) tends to occur at the upper right corner of the short transferred to the photoresist.
After exposure-development, generally, registration error between the wafer circuit pattern and a resist pattern is measured. Measurement of registration error is performed by a known method such as box-in-box method. More specifically, whether the patterns are superposed with high accuracy or not is determined referring to relative positions of registration mark formed by the same layer as the circuit pattern on the wafer and the registration mark formed on the resist pattern. When the registration error is within a tolerable range, the resist pattern is used as a mask and a film is etched. When the registration error exceeds the tolerable range, application, exposure and development of the photoresist are performed again.
In the conventional reticle, however, it is not possible to place registration mark 7 near the upper right corner of FIG. 15. Therefore, similar to the case of an alignment mark, position offset information of this corner is missed, resulting in a problem of degraded registration accuracy because of an error in shot magnification, an error in shot rotation or the like.
Even when analysis is performed using the result of registration inspection and exposure is performed with alignment corrected, it is not possible to calculate a value for correction of the alignment at the upper right portion of the shot, which leads to degraded registration accuracy.
In order to prevent degradation of registration accuracy, the reticle structure may be modified as shown in FIG. 20.
Referring to FIG. 20, in this structure, relatively wide dicing regions 303A are arranged on all four sides outside a prescribed rectangular region 302. Prescribed region 302 includes element forming regions 1A and 1B and a dicing region 303B positioned therebetween, similar to the example described above.
As relatively wide dicing regions 303A are arranged on all of the four sides, it becomes possible to arrange monitor mark regions such as alignment mark region 5 and registration accuracy measurement mark region 7 near all four corners of prescribed region 302. Therefore, degradation of registration accuracy resulting from missing monitor mark 5 or 7 at any corner of the prescribed region 302 is prevented.
In this case, however, the width W.sub.0 of dicing region 363A between the shots becomes wider and comes to occupy large area as shown in FIG. 21. Therefore, planer occupation of element forming regions 61A and 61B on the wafer is reduced, and yield of the semiconductor chip per wafer is reduced.